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FEATURES Handles all GSM Baseband Power Management Functions Four LDOs Optimized for Specific GSM Subsystems Charges Back-Up Capacitor for Real-Time Clock Charge Pump and Logic Level Translators for 3 V and 5 V GSM SIM Modules Narrow Body 4.4 mm 28-Lead TSSOP Package APPLICATIONS GSM/DCS/PCS Handsets TeleMatic Systems ICO/Iridium Terminals
GSM Power Management System ADP3404
FUNCTIONAL BLOCK DIAGRAM
VBAT
ADP3404
DIGITAL LDO VCC
RESET PWRONKEY ROWX POWER-UP SEQUENCING AND PROTECTION LOGIC
RTC LDO
VRTC
PWRONIN ANALOGON RESCAP
XTAL OSC LDO
VTCXO
GENERAL DESCRIPTION
The ADP3404 is a multifunction power management system IC optimized for GSM cell phones. The wide input voltage range of 3.0 V to 7.0 V makes the ADP3404 ideal for both single cell Li-Ion and three cell NiMH designs. The current consumption of the ADP3404 has been optimized for maximum battery life, featuring a ground current of only 230 A when the phone is in standby (digital LDO, analog LDO, and SIM card supply active). An undervoltage lockout (UVLO) prevents the startup when there is not enough energy in the battery. All four integrated LDOs are optimized to power one of the critical sub-blocks of the phone. Their novel anyCAP(R) architecture requires only very small output capacitors for stability, and the LDOs are insensitive to the capacitors' equivalent series resistance (ESR). This makes them stable with any capacitor, including ceramic (MLCC) types for space-restricted applications. A step-up converter is implemented to supply both the SIM module and the level translation circuitry to adapt logic signals for 3 V and 5 V SIM modules. Sophisticated controls are available for power-up during battery charging, keypad interface and charging of an auxiliary back-up capacitor for the real-time clock. These allow an easy interface between ADP3404, GSM processor, charger, and keypad. Furthermore, a reset circuit and a thermal shutdown function have been implemented to support reliable system design.
CHRON
ANALOG LDO
VCCA
SIMBAT CAP+ CAP SIMPROG SIMON SIMGND REF + RESETIN CLKIN DATAIO I/O CLK RST DGND LOGIC LEVEL TRANSLATION AGND BUFFER REFOUT CHARGE PUMP VSIM
anyCAP is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
ADP3404-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS1
Parameter SHUTDOWN SUPPLY CURRENT VBAT = Low (UVLO Low) VBAT = High (UVLO High) OPERATING GROUND CURRENT VCC, VRTC, VCCA, REFOUT On VCC, VRTC, VCCA, REFOUT and VSIM On All LDOs and VSIM On All LDOs and VSIM On UVLO CHARACTERISTICS UVLO On Threshold UVLO Hysteresis INPUT CHARACTERISTICS Input High Voltage PWRONIN and ANALOGON PWRONKEY Input Low Voltage PWRONIN and ANALOGON PWRONKEY PWRONKEY INPUT PULLUP RESISTANCE TO VBAT CHRON CHARACTERISTICS CHRON Threshold CHRON Hysteresis Resistance CHRON Input Bias Current ROWX CHARACTERISTICS ROWX Output Low Voltage ROWX Output High Leakage Current SHUTDOWN Thermal Shutdown Threshold2 Thermal Shutdown Hysteresis DIGITAL LDO (VCC) Output Voltage Line Regulation Load Regulation Output Capacitor3 ANALOG LDO (VCCA) Output Voltage Line Regulation Load Regulation Output Capacitor3 Dropout Voltage Ripple Rejection Output Noise Voltage VCC VCC VCC CO VCCA VCCA VCCA CO VDO VBAT/ VCCA VNOISE VT RIN IB VOL IIH Symbol IBAT
(-20 C TA +85 C, VBAT = 3 V to 7 V, CVBAT = CSIMBAT = CVSIM = 10 F, CVCC = CVCCA = 2.2 F, CVRTC = 0.1 F, CVTCXO = 0.22 F, CVCAP = 0.1 F, minimum loads applied on all outputs, unless otherwise noted.)
Conditions VBAT = 2.7 V VBAT = 3.6 V, VRTC On
Min
Typ 3 12 175 230 260 15 3.2 200
Max 20 30 240 340 400
Unit A A A A A mA V mV
IGND Minimum Loads, VBAT = 3.6 V Minimum Loads, VBAT = 3.6 V Minimum Loads, VBAT = 3.6 V Maximum Loads, VBAT = 3.6 V VBATUVLO
3.3
VIH 2 0.7 VIL 0.4 0.3 15 2.38 108 20 2.48 125 25 2.58 138 0.5 0.4 1 V VBAT V k V k A V A VBAT V V
2.38 < CHRON < VT CHRON > VT PWRONKEY = Low IOL = 200 A PWRONKEY = High V(ROWX) = 5 V Junction Temperature Junction Temperature Line, Load, Temp 3 V < VBAT < 7 V, Min Load 50 A < ILOAD < 100 mA, VBAT = 3.6 V
160 35 2.400 2.450 2.500 2 15
C C V mV mV F
2.2 Line, Load, Temp 3 V < VBAT < 7 V, Min Load 200 A < ILOAD < 130 mA, VBAT = 3.6 V VO = VINITIAL - 100 mV ILOAD = 130 mA f = 217 Hz (t = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 130 mA, VBAT = 3.6 V 2.710 2.765 2.820 2 15 215 65 70 75
V mV mV F mV dB V rms
2.2
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Parameter CRYSTAL OSCILLATOR LDO (VTCXO) Output Voltage Line Regulation Load Regulation Output Capacitor3 Dropout Voltage Ripple Rejection Output Noise Voltage VOLTAGE REFERENCE (REFOUT) Output Voltage Line Regulation Load Regulation Ripple Rejection Maximum Capacitive Load Output Noise Voltage REAL-TIME CLOCK LDO/BATTERY CHARGER (VRTC) Maximum Output Voltage Current Limit Off Reverse Leakage Current SIM CHARGE PUMP (VSIM) Output Voltage for 5 V SIM Modules Output Voltage for 3 V SIM Modules GSM/SIM LOGIC TRANSLATION (GSM INTERFACE) Input High Voltage (SIMPROG, SIMON, RESETIN, CLKIN) Input Low Voltage (SIMPROG, SIMON, RESETIN, CLKIN) DATAIO Symbol VTCXO VTCXO VTCXO CO VDO VBAT/ VTCXO VNOISE Conditions Line, Load, Temp 3 V < VBAT < 7 V, Min Load 100 A < ILOAD < 5 mA, VBAT = 3.6 V VO = VINITIAL - 100 mV ILOAD = 5 mA f = 217 Hz (t = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 5 mA, VBAT = 3.6 V Line, Load, Temp 3 V < VBAT < 7 V, Min Load 0 A < ILOAD < 50 A, VBAT = 3.6 V f = 217 Hz (t = 4.6 ms), VBAT = 3.6 V f = 10 Hz to 100 kHz VBAT = 3.6 V Min 2.710 Typ 2.765 2 1 Max 2.820 Unit V mV mV F mV dB V rms
0.22 150 65 72 80
VREFOUT VREFOUT VREFOUT VBAT/ VREFOUT CO VNOISE
1.192
1.210 2 0.5 75
1.228
V mV mV dB pF V rms
65 100
40
VRTC IMAX IL VSIM VSIM
ILOAD 10 A 2.0 V < VBAT < UVLO 0 mA ILOAD 10 mA SIMPROG = High 0 mA ILOAD 6 mA SIMPROG = Low
2.400
2.450 175
2.500 1
V A A V V
4.70 2.82
5.00 3.00
5.30 3.18
VIH VIL VIL VOL (I/O) = 0.4 V, IOL (I/O) = 1 mA VOL (I/O) = 0.4 V, IOL (I/O ) = 0 mA IIH, IOH = 10 A VIL = 0 V VIL (I/O) = 0.4 V
VCC - 0.6 0.6 0.230 0.335 VCC - 0.4 -0.9 0.420 24
V V V V V mA V k
DATAIO Pull-Up Resistance to VCC
VIH, VOH IIL VOL RIN
16
20
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ADP3404-SPECIFICATIONS
Parameter SIM INTERFACE VSIM = 5 V RST RST CLK CLK I/O I/O I/O I/O VSIM = 3 V RST RST CLK CLK I/O I/O I/O I/O I/O Pull-Up Resistance to VSIM Max Frequency (CLK) Prop Delay (CLK) Output Rise/Fall Times (CLK) Output Rise/Fall Times (I/O, RST) Duty Cycle (CLK) RESET GENERATOR (RESET) Output High Voltage Output Low Voltage Delay Time per Unit Capacitance Applied to RESCAP Pin Symbol Conditions Min Typ Max Unit VOL VOH VOL VOH VIL VIH, VOH IIL VOL VOL VOH VOL VOH VIL VIH, VOH IIL VOL RIN fMAX tD tR, tF tR, tF D I = +200 A I = -20 A I = +200 A I = -20 A IIH, IOH = 20 A VIL = 0 V IOL = 1 mA DATAIO 0.23 V I = +200 A I = -20 A I = +20 A I = -20 A IIH, IOH = 20 A VIL= 0 V IOL = 1 mA DATAIO 0.23 V CL = 30 pF CL = 30 pF CL = 30 pF D CLKIN = 50% f = 5 MHz IOH = -15 A IOL = -15 A 0.6 VSIM - 0.7 0.5 0.7 VSIM 0.4 VSIM - 0.4 -0.9 0.4 V V V V V V mA V
0.2 0.8 0.7 VSIM 0.2 VSIM 0.4 VSIM - 0.4 -0.9 0.4 8 5 10 30 9 47 12 50 18 1 53
VSIM VSIM
V V V V V V mA V k MHz ns ns s %
VOH VOL tD
VCC - 0.3 0.3 1.0
V V ms/nF
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods . 2 This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125 C. Operation beyond 125C could cause permanent damage to the device. 3 Required for stability. Specifications subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS
Voltage on Any Pin with Respect to Any GND Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +10 V Voltage on Any Pin May Not Exceed VBAT, with the Following Exceptions: VRTC, VSIM, CAP+, PWRONIN, I/O, CLK, RST Storage Temperature Range . . . . . . . . . . . . -65C to +150C Operating Temperature Range . . . . . . . . . . . -20C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C JA, Thermal Impedance (TSSOP-28) . . 4-Layer Board 68C/W JA, Thermal Impedance (TSSOP-28) . . 6-Layer Board 62C/W Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300C
*This is a stress rating only, operation beyond these limits can cause the device to be permanently damaged.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Mnemonic RESCAP DGND VTCXO RESET REFOUT VCCA AGND VBAT VCC PWRONKEY ANALOGON PWRONIN ROWX CHRON VRTC CAP- SIMBAT DATAIO RESETIN CLKIN SIMGND I/O RST SIMPROG SIMON CLK VSIM CAP+
Function Reset Delay Timing Cap Digital Ground Crystal Oscillator Low Dropout Regulator Main Reset Reference Output Analog Low Dropout Regulator Analog Ground Battery Input Voltage Digital Low Dropout Regulator Power-On/-Off Key VTCXO Enable Power On/Off Signal from Microprocessor Microprocessor Keyboard Output Charger On/Off Input Real-Time Clock Supply/Coin Cell Battery Charger Negative Side of Boost Capacitor Battery Input for the SIM Charge Pump Non-Level-Shifted Bidirectional Data I/O Non-Level-Shifted SIM Reset Non-Level-Shifted Clock Charge Pump Ground Level-Shifted Bidirectional SIM Data Input/Output Level-Shifted SIM Reset VSIM Programming: Low = 3 V, High = 5 V VSIM Enable Level-Shifted SIM Clock SIM Supply Positive Side of Boost Capacitor
PIN CONFIGURATION
RESCAP 1 DGND 2 VTCXO 3 RESET 4 REFOUT 5 VCCA 6 AGND 7 VBAT 8 VCC 9 PWRONKEY 10 ANALOGON 11 PWRONIN 12 ROWX 13 CHRON 14 NARROW BODY TSSOP-28
28 27 26 25 24 23
CAP+ VSIM CLK SIMON SIMPROG RST I/O
ADP3404
22
(Not To Scale) 21 SIMGND 20 CLKIN
19 18 17 16 15
RESETIN DATAIO SIMBAT CAP- VRTC
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option RU-28
ADP3404ARU -20C to +85C 28-Lead TSSOP
25 26 27 28
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3404 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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Table I. LDO Control Logic
Inputs UVLO L H H H H H CHRON X H X L L L PWRONKEY X X L H H H PWRONIN X X X L H H ANALOGON X X X X L H VRTC Off On On On On On VCC Off On On Off On On
Outputs VCCA Off On On Off On On REFOUT Off On On Off On On VTCXO Off On On Off Off On
X = Don't care Bold denotes the active control signal.
Table II. VSIM Control Logic
Inputs VCC Off On On On On RESET L L H H H SIMON X X L H H SIMPROG X X X L H
Outputs VSIM Off Off Off 3V 5V
X = Don't care
VBAT
ADP3404
DIGITAL LDO VBAT VREF OUT GND PG DGND VCC 2.45V
20k
UVLO UVLO
ADJ
EN
PWRONKEY ROWX OVER TEMP
POWER GOOD RTC LDO VBAT OUT GND
VRTC 2.45V
PWRONIN RESCAP
EN
RESET GENERATOR
CHARGER ON THRESHOLD
RESET XTAL OSC LDO VBAT VREF EN GND OUT VTCXO 2.765V
CHRON ANALOGON SIMBAT CAP+ CAP- SIMPROG SIMON SIMGND RESETIN CLKIN DATAIO
ANALOG LDO EN CHARGE PUMP 3V/5V EN GND VBAT VREF EN GND OUT VCCA 2.765V
LOGIC LEVEL TRANSLATION + 1.210V
EN REF BUFFER
REFOUT
AGND
I/O CLK RST
VSIM
Figure 1. Functional Block Diagram
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Typical Performance Characteristics-ADP3404
350 200 180 300 PWRONIN, SIMON, AND ANALOGON 140
IGND - A
160
+85 C
PWRONIN AND SIMON
IRTC - A
250
120 100 80 60 40 20 20 C +25 C
200 PWRONIN 150
100
3
4
5 VBAT - V
6
7
0
0
0.3
0.6
0.9
1.2 1.5 VRTC - V
1.8
2.1
2.4
2.7
TPC 1. Ground Current vs. Battery Voltage
TPC 4. RTC I/V Characteristic
160 MLCC CAPS 140 3.2 VBAT 100mV/DIV
DROPOUT VOLTAGE - mV
120 100 80 60 40 20 0 3.0 VOLTAGE VCC 10mV/DIV
VCCA 10mV/DIV
VTCXO 10mV/DIV
0
20
40
60 80 100 LOAD CURRENT - mA
120
140 TIME - 100 s/DIV
TPC 2. VCCA Dropout Voltage vs. Load Current
TPC 5. Line Transient Response, Maximum Loads
80
MLCC CAPS
70
3.2
VBAT (100mV/DIV)
DROPOUT VOLTAGE - mV
60 50 40 30 20 10 0
VOLTAGE
3.0 VCC (10mV/DIV)
VCCA (10mV/DIV)
VTCXO (10mV/DIV)
0
1
2 3 LOAD CURRENT - mA
4
5
TIME - 100 s/DIV
TPC 3. VTCXO Dropout Voltage vs. Load Current
TPC 6. Line Transient Response, Minimum Loads
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MLCC CAPS ILOAD I = 100mA I = 200 A
PWRONIN AND ANALOGON (2V/DIV)
VOLTAGE - 20mV/DIV
VOLTAGE
VCC
VCCA (100mV/DIV)
REFOUT (100mV/DIV) VCC (100mV/DIV)
VTCXO (100mV/DIV)
TIME - 200 s/DIV
TIME - 50 s/DIV
TPC 7. VCC Load Step
TPC 10. Turn-On Transients, Maximum Loads
80
MLCC CAPS ILOAD I = 130mA
70 RIPPLE REJECTION - dB 60
VCCA
VTCXO
VOLTAGE - 20mV/DIV
I = 50 A
REFOUT 50 40 30 20 10 0 MLCC OUTPUT CAPS VBAT = 3.2V, FULL LOADS VCC
VCCA
1
10
TIME - 100 s/DIV
100 1k FREQUENCY - Hz
10k
100k
TPC 8. VCCA Load Step
TPC 11. Ripple Rejection vs. Frequency
80 REFOUT 70 PWRONIN AND ANALOGON (2V/DIV) VCCA (100mV/DIV)
RIPPLE REJECTION - dB
60 50 VCC 40 30 VTCXO 20 10 0 2.5 FREQUENCY = 217Hz MAX LOADS 2.6 2.7 2.8 2.9 3.0 VBAT - V 3.1 3.2 3.3 VCCA
VOLTAGE
VTCXO (100mV/DIV)
VCC (100mV/DIV)
TIME - 50 s/DIV
TPC 9. Turn-On Transients, Minimum Loads
TPC 12. Ripple Rejection vs. Battery Voltage
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Hz
600 FULL LOAD MLCC CAPS 500 VCCA 400 TCXO
VOLTAGE SPECTRAL NOISE DENSITY - nV/
These functions have traditionally been done either as a discrete implementation or as a custom ASIC design. ADP3404 combines the benefits of both worlds by providing an integrated standard product solution where every block is optimized to operate in a GSM environment while maintaining a cost competitive solution. Figure 2 shows the external circuitry associated with the ADP3404. Only a few support components, mainly decoupling capacitors, are required.
Input Voltage
300
200 REF 100
0 10
100
1k FREQUENCY - Hz
10k
100k
TPC 13. Output Noise Density
THEORY OF OPERATION
The ADP3404 is a power management chip optimized for use with GSM baseband chipsets in handset applications. Figure 1 shows a block diagram of the ADP3404. The ADP3404 contains several blocks: * Four Low Dropout Regulators (Digital, Analog, Crystal Oscillator, Real-Time Clock) * Reset Generator * Buffered Precision Reference * SIM Interface Logic Level Translation (3 V/5 V) * SIM Voltage Supply * Power On/Off Logic * Undervoltage Lockout
The input voltage range for ADP3404 is 3 V to 7 V and optimized for a single Li-Ion cell or three NiMH/NiCd cells. The thermal impedance (JA) of the ADP3404 is 62C/W for 6-layer boards. The charging voltage for a high capacity NiMH cell can be as high as 5.5 V. Power dissipation should be calculated at maximum ambient temperatures and battery voltage in order not to exceed the 125C maximum allowable junction temperature. Figure 3 shows the maximum total LDO output current as a function of ambient temperature and battery voltage. However, high battery voltages normally occur only when the battery is being charged and the handset is not in conversation mode. In this mode there is a relatively light load on the LDOs. A fully charged Li-Ion battery is 4.25 V, where the LDOs deliver the maximum 240 mA up to the max 85C ambient temperature.
ANALOG GND DIGITAL AND SIM GND 100nF
1 2 3
RESCAP DGND VTCXO RESET REFOUT VCCA AGND VBAT VCC PWRONKEY ANALOGON PWRONIN ROWX CHRON TSSOP-28
CAP+ 28 VSIM 27 CLK 26 SIMON 25 SIMPROG 24 10 F CLK TO SIM CARD GSM PROCESSOR RST TO SIM CARD I/O TO SIM CARD
0.22 F
4 5
100nF
10 2.2 F
6 7 8
ADP3404
RST 23 I/O 22 SIMGND 21 CLKIN 20
10 F 1 LI-ION OR 3 NIMH 2.2 F
9 10 11
RESETIN 19 DATAIO 18 SIMBAT 17 CAP-
16
SIM PINS OF GSM PROCESSOR 100nF
GSM PROCESSOR CHARGER INPUT
12 13 14
VRTC 15 100nF
R1
R2
CAPACITORTYPE BACK-UP COIN CELL
10 F
Figure 2. Typical Application Circuit
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300 6-LAYER BOARD JA = 62 C/W 250
TOTAL LDO CURRENT - mA
VBAT = 5V VBAT = 5.5V
200 VBAT = 6V VBAT = 7V 150
The ADP3404 supplies current both for charging the coin cell and for the RTC module when the digital supply is off. The nominal charging voltage is 2.45 V, which ensures long cell life while obtaining in excess of 90% of the nominal capacity. In addition, it features a very low quiescent current (10 A) since this LDO is running all the time, even when the handset is switched off. It also has reverse current protection with low leakage which is needed when the main battery is removed and the coin cell supplies the RTC module.
Reference Output (REFOUT)
100
50
0
20
0
20 40 60 AMBIENT TEMPERATURE - C
80 85
The reference output is a low noise, high precision reference with a guaranteed accuracy of 1.5% over temperature. The reference can be fed to the baseband converter, such as the AD6425, improving the absolute accuracy of the converters from 5% to 1.5%. This significantly reduces calibration time needed for the baseband converter during production.
SIM Interface
Figure 3. Total LDO Load Current vs. Temperature and VBAT
Low Dropout Regulators (LDOs)
The ADP3404 high-performance LDOs are optimized for their given functions by balancing quiescent current, dropout voltage, line/load regulation, ripple rejection, and output noise. 2.2 F tantalum or MLCC ceramic capacitors are recommended for use with the digital and analog LDOs, and 0.22 F for the TCXO LDO.
Digital LDO (VCC)
The SIM interface generates the needed SIM voltage--either 3 V or 5 V, dependent on SIM type, and also performs the needed logic level translation. Quiescent current is low, as the SIM card will be powered all the time. Note that DATAIO and I/O have integrated pull-up resistors as shown in Figure 5. See Table II for the control logic of the charge pump output, VSIM.
ADP3404
VCC RESETIN LEVEL SHIFT VCC CLKIN VCC VSIM LEVEL SHIFT VSIM CLK VSIM RST
The digital LDO (VCC) supplies all the digital circuitry in the handset (baseband processor, baseband converter, external memory, display, etc.). The LDO has been optimized for very low quiescent current (30 A maximum) at light loads as this LDO is on at all times.
Analog LDO (VCCA)
This LDO has the same features as the digital LDO. It has furthermore been optimized for good low frequency ripple rejection for use with analog sections in order to reject the ripple coming from the RF power amplifier. VCCA is rated to 130 mA load which is sufficient to supply the complete analog section of a baseband converter such as the AD6421/AD6425, including a 32 earpiece.
TCXO LDO (VTCXO)
DATAIO
I/O
Figure 5. Schematic for Level Translators
Power-On/-Off
The TCXO LDO is intended as a supply for temperature compensated crystal oscillator, which needs its own ultralow noise supply. The output current is rated to 5 mA for the TCXO LDO.
RTC LDO (VRTC)
ADP3404 handles all issues regarding power-on/-off of the handset. It is possible to turn on the ADP3404 in three different ways: * Pulling PWRONKEY Low * Pulling PWRONIN High * CHRON exceeds threshold Pulling PWRONKEY key low is the normal way of turning on the handset. This will turn on all the LDOs as long as PWRONKEY is held low. The microprocessor then starts and pulls PWRONIN high after which PWRONKEY can be released. PWRONIN going high will also turn on the handset. This is the case when the alarm in the RTC module expires. An external charger can also turn on the phone. The turn-on threshold and hysteresis can be programmed via external resistors to allow full flexibility with any external charger and battery chemistry. These resistors are referred to as R1 and R2 in Figure 2.
The RTC LDO charges a capacitor-type backup coin cell to run the real-time clock module. It has been targeted to charge electric double layer capacitors such as the PAS621 from Kanebo. The PAS621 has a small physical size (6.8 mm diameter) and a nominal capacity of 0.3 F, giving many hours of backup time.
ADP3404
GSM PROCESSOR
VRTC COIN CELL
VRTC
RTC MODULE
PWRONIN
PWRON
Figure 4. Connecting VRTC and PWRONIN to the Chipset
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Undervoltage Lockout (UVLO) LDO Capacitor Selection
The UVLO function in the ADP3404 prevents startup when the initial voltage of the main battery is below the 3.2 V threshold. If the battery is this low with no load, there will be little or no capacity left. When the battery is greater than 3.2 V, as with the insertion of a fresh battery, the UVLO comparator trips, the RTC LDO is enabled, and the threshold is reduced to 3.0 V. This allows the handset to start normally until the battery voltage decays to 3.0 V open circuit. Once the 3.2 V threshold is exceeded, the RTC LDO is enabled. If, however, if the backup coin cell is not connected, or is damaged or discharged below 1.5 V, the RTC LDO will not start on its own. In this situation, the RTC LDO will be started by enabling the VCC LDO. Once the system is started, i.e., the phone is turned on and the VCC LDO is up and running, the UVLO function is entirely disabled. The ADP3404 is then allowed to run down to very low battery voltages, typically around 2 V. The battery voltage is normally monitored by the microprocessor and usually shuts the phone off at around 3.0 V. If the phone is off, i.e., the VCC LDO is off, and the battery voltage drops below 3.0 V, the UVLO circuit disables startup and the RTC LDO. This is implemented with very low quiescent current, typically 3 A, to protect the main battery against any damage. NiMH batteries can reverse polarity if the 3-cell battery voltage drops below 3.0 V and a current of more than about 40 A continues to flow. Lithium ion batteries will lose their capacity, although the built-in safety circuits normally present in these cells will most likely prevent any damage.
RESET
The performance of any LDO is a function of the output capacitor. The digital and analog LDOs require a 2.2 F capacitor and the TCXO LDO requires a 0.22 F capacitor. Larger values may be used, but the overshoot at startup will increase slightly. If a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application. All the LDOs are stable with a wide range of capacitor types and ESR due to Analog Devices' anyCAP technology. The ADP3404 is stable with extremely low ESR capacitors (ESR ~ 0), such as multilayer ceramic capacitors, but care should be taken in their selection. Note that the capacitance of some capacitor types show wide variations over temperature or with dc voltage. A good quality dielectric, X7R or better, is recommended. The RTC LDO has a rechargeable coin cell or an electric doublelayer capacitor as a load, but a 0.1 F ceramic capacitor is recommended for stability and best performance.
Charge Pump Capacitor Selection
For the input (SIMBAT) and output (VSIM) of the SIM charge pump, use 10 F low ESR capacitors. The use of low ESR capacitors improves the noise and efficiency of the SIM charge pump. Multilayer ceramic chip capacitors provide the best combination of low ESR and small size but may not be cost effective. A lower cost alternative may be to use a 10 F tantalum capacitor with a small (1 F to 2 F) ceramic capacitor in parallel. For the lowest ripple and best efficiency, use a 0.1 F, ceramic capacitor for the charge pump flying capacitor (CAP+ and CAP-). A good quality dielectric, such as X7R is recommended.
Setting the Charger Turn-On Threshold
ADP3404 contains reset circuitry that is active both at power-up and at power-down. RESET is held low at power-up. An internal power-good signal starts the reset delay. The delay is set by an external capacitor on RESCAP:
tRESET = 1.0 ms/nF x CRESCAP
The ADP3404 can be turned on when the charger input exceeds a programmable threshold voltage. The charger's threshold and hysteresis are set by selecting the values for R1 and R2 shown in Figure 2. The turn-on threshold for the charger is calculated using:
R2 + RHYS VCHR = x R1 + 1 x VT R2 x RHYS
A 100 nF capacitor will produce a 100 ms reset time. At power-off, RESET will be kept low to prevent any spurious microprocessor starts. The current capability of RESET is low (a few hundred nA) when VCC is off, to minimize power consumption. Therefore, RESET should only be used to drive a single CMOS input. When VCC is on, RESET will drive about 15 A.
Overtemperature Protection
Where VT is the CHRON threshold voltage and RHYS is the CHRON hysteresis resistance. The hysteresis is determined using:
The maximum die temperature for ADP3404 is 125C. If the die temperature exceeds 160C, the ADP3404 will disable all the LDOs except the RTC LDO, which has very limited current capabilities. The LDOs will not be re-enabled before the die temperature is below 125C, regardless of the state of PWRONKEY, PWRONIN, and CHRON. This ensures that the handset will always power-off before the ADP3404 exceeds its absolute maximum thermal ratings.
APPLICATIONS INFORMATION Input Capacitor Selection
VHYS =
VT x R1 RHYS
Combining the above equations and solving for R1 and R2 gives the following formulas:
R1 =
R2 =
RHYS x VHYS VT
For the input voltage, VBAT, of the ADP3404, a local bypass capacitor is recommended. Use a 5 F to 10 F, low ESR capacitor. Multilayer ceramic chip capacitors provide the best combination of low ESR and small size, but may not be cost effective. A lower cost alternative may be to use a 5 F to 10 F tantalum capacitor with a small (1 F to 2 F) ceramic in parallel.
R1 x RHYS VCHR - 1 x RHYS - R1 VT
Example: R1 = 10 k and R2 = 30.2 k gives a charger threshold (not counting the drop in the power Schottky diode) of 3.5 V 160 mV with a 200 mV 30 mV hysteresis.
REV. 0
-11-
ADP3404
Charger Diode Selection Printed Circuit Board Layout Considerations
2. SIM input and output capacitors should be returned to the SIMGND and kept as close as possible to the ADP3404 to minimize noise. Traces to the SIM charge pump capacitor should be kept as short as possible to minimize noise. 3. VCCA and VTCXO capacitors should be returned to AGND. 4. VCC and VRTC capacitors should be returned to DGND. 5. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds, and tie them together at a single point, preferably close to the battery return.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Thin Shrink Small Outline (TSSOP) (RU-28)
0.386 (9.80) 0.378 (9.60)
28
15
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 14
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
-12-
REV. 0
PRINTED IN U.S.A.
C02375-2.5-4/01(0)
The diode shown in Figure 2 is used to prevent the battery from discharging into the charger turn-on setting resistors, R1 and R2. A Schottky diode is recommended to minimize the voltage difference from the charger to the battery and the power dissipation. Choose a diode with a current rating high enough to handle both the battery charging current and the current the ADP3404 will draw if powered up during charging. The battery charging current is dependent on the battery chemistry, and the charger circuit. The ADP3404 current will be dependent on the loading.
Use the following general guidelines when designing printed circuit boards: 1. Split the battery connection to the VBAT and SIMBAT pins of the ADP3404. Use separate traces for each connection and locate the input capacitors as close to the pins as possible.

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